Semiconductor device and method of manufacturing the same

ABSTRACT

An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method ofmanufacturing the same. In particular, the present invention relates toa semiconductor device whose drain-to-source breakdown voltage, V_(DSS),is increased and a method of manufacturing the same.

2. Description of the Related Art

By referring to FIG. 10 and FIGS. 11A to 11C, a conventionalsemiconductor device and a method of manufacturing the same will bedescribed by taking a MOSFET as an example.

As shown in FIG. 10, a drain region 20 is provided, for example, bylaminating an n type epitaxial layer 22 on an n+ type siliconsemiconductor substrate 21, and a plurality of p type channel regions 24are provided on a surface of the drain region 20. A gate electrode 33 isprovided on a portion on the surface of the n type epitaxial layerbetween the two p type channel regions 24 which are adjacent to eachother, with a gate insulation film 31 interposed therebetween.Peripheries of the gate electrode 33 are covered with an interlayerinsulating film 36. Additionally, n+ type source regions 35, beingformed in the surface of the channel regions 24, are in contact with asource electrode 38.

As a technology for the above-mentioned MOSFET of a so-called planarstructure, one in which an n type impurity layer 40 having a higherimpurity concentration than the epitaxial layer 22 is arranged on thesurface of the n− type epitaxial layer 22 between the two adjacent ptype channel regions 24 is also known. In case of a MOSFET whosebreakdown voltage is 600 V, it is possible to increase the impurityconcentration of the n type impurity layer 40 to approximately 1×10¹⁶cm⁻³. This technology brings about an effect of reducing adrain-to-source resistance when the MOSFET is in the ON state. Thistechnology is described, for instance, in Japanese Patent ApplicationPublication No. 2622378.

By referring to FIGS. 11A to 11C, the method of manufacturing theabove-mentioned MOSFET will be described.

A substrate, obtained, for example, by laminating the n− type epitaxiallayer 22 on the n+ type silicon semiconductor substrate 21, forms thedrain region 20. Ions of an n type impurity (for example, phosphor: P)are implanted into an entire surface of the n− type epitaxial layer(FIG. 11A). Thereafter, the gate oxide film 31 and the gate electrode 33are formed. Then, ions of a p type impurity (for example, boron: B) areimplanted, by using the gate electrode 33 as a mask (FIG. 11B).Subsequently, by diffusing the n type impurity and the p type impuritythrough a thermal treatment, the n type impurity layer 40 and thechannel regions 24 are formed. On the surface of the channel regions 24,the source regions 35 are formed (FIG. 11C). Then, the gate electrode 33is covered with the interlayer insulating film and the source electrode(not illustrated) is formed.

In the MOSFET shown in FIG. 10, when the MOSFET is in the ON state, thedrain region 20 below the gate electrode 33 works as a region forcausing an electric current to flow in a direction perpendicular to thesubstrate. That is, the n type impurity layer 40 having a high impurityconcentration is arranged in a portion (hereinafter, referred to as a πportion 45) on the surface of the drain region 20 between each twoadjacent ones of the channel regions 24 because it is preferable that,when the MOSFET is in the ON state, a resistance of the drain region 20be low.

On the other hand, when the MOSFET is in the OFF state, adrain-to-source voltage is applied and a reverse bias is generated. As aresult, a depletion layer 50 extends from pn junctions with the channelregion 24 and generates a depletion state, whereby the breakdown voltageis increased. That is, it is preferable that the impurity concentrationof the π portion 45 be higher in order to allow the drain region 20 tohave a lower resistance. However, if the impurity concentration of theπ60 portion 45 increases more than necessarily, the extension width ofthe depletion layer 50 becomes narrow as shown in the dotted line ofFIG. 10, whereby there arises a problem that a breakdown voltage isdeteriorated.

Additionally, because a curvature from a bottom to a side surfacebecomes large in each of the channel regions 24 formed throughdiffusion, the interval between the two adjacent ones of the channelregions 24 becomes wide in vicinity of the bottoms thereof. That is, thedepletion layer 50 pinching off sufficiently in vicinity of the topsurface of the channel regions 24 does not sufficiently pinch off invicinity of the bottoms thereof, whereby there arises a problem that abreakdown tends to occur in corner portions (refer to a region “a” inFIG. 10) of each of the channel regions 24.

Furthermore, because the ion implantation of the n type impurity layer40 is performed before the formation of the gate electrode (refer toFIG. 11A), the n type impurity (for example, phosphor) is diffusedthrough a thermal treatment during the formation of the gate electrode33. Therefore, after the formation of the channel regions 24, a depth ofeach of the channel regions 24 tends to be shallower than that of the πportion 45, whereby a reduced V_(DSS) becomes a problem.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor device that includes asemiconductor substrate of a first general conductivity type, asemiconductor layer of the first general conductivity type disposed on asurface of the semiconductor substrate so as to provide a drain region,two channel regions of a second general conductivity type disposed onthe semiconductor layer, an impurity region of the first generalconductivity type disposed between the two channel regions, an junctioninterface between the impurity region and one of the channel regionsbeing perpendicular to the surface of the semiconductor substrate, aninsulating film disposed on the impurity region, a gate electrodedisposed on the insulating film, and a source region of the firstgeneral conductivity type formed in a surface of each of the channelregions.

The present invention also provides a method of manufacturing asemiconductor device. The method includes providing a deviceintermediate comprising a semiconductor substrate of a first generalconductivity type, a semiconductor layer of the first generalconductivity type disposed on the semiconductor substrate and a firstinsulating film disposed on the semiconductor layer, forming a gateelectrode on the first insulating film, forming an impurity region ofthe first general conductivity type in the semiconductor layer under thegate electrode after the formation of the gate electrode, forming twochannel regions of a second general conductivity type in thesemiconductor layer so that the impurity region connects the two channelregions, forming a source region of the first general conductivity typein each of the channel regions, and forming a second insulating filmcovering the gate electrode.

The present invention further provides a method of manufacturing asemiconductor device. The method includes providing a deviceintermediate comprising a semiconductor substrate of a first generalconductivity type, a semiconductor layer of the first generalconductivity type disposed on a surface of the semiconductor substrateand a first insulating film disposed on the semiconductor layer, formingon the first insulation film a gate electrode having an opening therein,implanting a first impurity for the first general conductivity type intopart of the semiconductor layer through the opening of the gateelectrode, implanting a second impurity for the second generalconductivity type into part of the semiconductor layer that is outsidethe gate electrode, heating the device intermediate so that the firstand second impurities are diffused so as to form an impurity region anda channel region that have an junction interface perpendicular to thesurface of the semiconductor substrate, forming a source region of thefirst general conductivity type in the channel region, and forming asecond insulating film covering the gate electrode.

The present invention further provides a semiconductor device thatincludes a semiconductor substrate of a first general conductivity type,a semiconductor layer of the first general conductivity type disposed ona surface of the semiconductor substrate so as to provide a drainregion, two channel regions of a second general conductivity typedisposed on the semiconductor layer, an impurity region of the firstgeneral conductivity type disposed between the two channel regions so asto connect the two channel regions, an insulating film disposed on theimpurity region, a gate electrode disposed on the insulating film andcomprising a first gate electrode portion and a second gate electrodeportion that are disposed on the impurity region between the two channelregions, the first gate electrode portion being at least partiallyseparated from the second gate electrode portion, and a source region ofthe first general conductivity type formed in a surface of each of thechannel regions.

The present invention further provides a semiconductor device thatincludes a semiconductor substrate of a first general conductivity type,a semiconductor layer of the first general conductivity type disposed ona surface of the semiconductor substrate so as to provide a drainregion, two channel regions of a second general conductivity typedisposed on the semiconductor layer, each of the channel regions beingelongated in a direction, an impurity region of the first generalconductivity type disposed between the two elongated channel regions,the impurity region being elongated in the direction, an insulating filmdisposed on the elongated impurity region and channel regions, a gateelectrode disposed on the insulating film and having a slit elongated inthe direction but not reaching an edge portion of the gate electrode,and a source region of the first general conductivity type formed in asurface of each of the channel regions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are cross-sectional views and FIG. 1C is a perspectiveview explaining a semiconductor device of a first and a secondembodiments of the invention.

FIG. 2 is a characteristic chart explaining the semiconductor device ofthe first and the second embodiments of the invention.

FIG. 3 is a cross-sectional view explaining a method of manufacturingthe semiconductor device of the first and the second embodiments of theinvention.

FIG. 4 is a cross-sectional view explaining the method of manufacturingthe semiconductor device of the first and the second embodiments of theinvention.

FIG. 5 is a cross-sectional view explaining the method of manufacturingthe semiconductor device of the first and the second embodiments of theinvention.

FIG. 6 is a cross-sectional view explaining the method of manufacturingthe semiconductor device of the first and the second embodiments of theinvention.

FIG. 7 is a cross-sectional view explaining the method of manufacturingthe semiconductor device of the first and the second embodiments of theinvention.

FIGS. 8A and 8B are cross-sectional views explaining the method ofmanufacturing the semiconductor device of the first and the secondembodiments of the invention.

FIG. 9 is a cross-sectional view explaining the method of manufacturingthe semiconductor device of the first and the second embodiments of theinvention.

FIG. 10 is a cross-sectional view explaining a conventionalsemiconductor device.

FIGS. 11A to 11C are cross-sectional views explaining a method ofmanufacturing the conventional semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will be described with referenceto FIGS. 1 to 9 by taking an n-channel MOSFET as an example.

FIGS. 1A and 1B are cross-sectional views indicating a structure of aMOSFET of a first embodiment of the invention. FIGS. 1A and 1B arecross-sectional views showing a single cell of the MOSFET, and pluralones of the cells are arranged to constitute the MOSFET. FIG. 1C shows aperspective view of the MOSFET cut at the section shown in FIG. 1A.

The MOSFET includes a semiconductor substrate 1, a semiconductor layer2, channel regions 4, a one conductive type impurity region 14, a gateelectrode 13, a gate insulation film 11, an interlayer insulating film16, and source regions 15.

A substrate obtained, for example, by laminating the n type epitaxiallayer 2 on the n+ type silicon semiconductor substrate 1 is prepared,and thus a drain region 10 is provided. The p type channel regions 4 areprovided on the surface of the n− type epitaxial layer 2. The channelregions 4 are a plurality of p type impurity regions provided on the n−type epitaxial layer 2 through an ion implantation and an ion diffusion.Note that, in some cases, a low-resistance layer 1 is formed on thesemiconductor layer 2 by the impurity diffusion.

The gate oxide film 11 is provided on the surface of the n− typeepitaxial layer 2, and the gate electrode 13 is arranged on the gateoxide film 11. The interlayer insulating film 16 is provided over thegate electrode 13. Peripheries of the gate electrode 13 are covered withthe gate oxide film 11 and the interlayer insulating film 16.

The cell shown in FIGS. 1A-1C includes the gate electrode 13 that has aseparation hole 12 elongated in the longitudinal direction of the gateelectrode 13. The width of the separation is L_(KT). In this embodiment,the separation hole 12 does not completely separate the gate electrode13, and both ends of the gate electrode 13 are left intact. As amodification, one end of the gate electrode 13 may be separatedcompletely while another end holds the separated portions of the gateelectrode together. As a further modification, the gate electrode may becompletely separated. In either embodiment, all the gate electrode 13are connected together outside the MOSFET element region on which thecells are formed. As shown in FIG. 1C, the separated gate electrodes 13a and 13 b are covered by a single interlayer insulating film 16. Bothof the separated gate electrodes 13 a and 13 b have an equal widthL_(g). As shown in FIG. 1C, the channel region 4 also has an elongatedform and is aligned with a corresponding gate electrode.

The source regions 15 are highly concentrated n type impurity regionprovided in the channel regions 4. Each of the source region 15 isplaced in a portion of a region, a part of which is under the gateelectrode 13, and the rest being outward thereof. The source regions 15are in contact with a source electrode 18 through contact holes CHbetween the interlayer insulating film 16.

In a region under the gate electrode 13 on the surface of the n− typeepitaxial layer 2, an n type impurity region 14 is provided. Sidesurfaces of the n type impurity region 14 and side surfaces of each ofthe channel region 4 adjacent thereto form a substantially perpendicularjunction surfaces. Additionally, a bottom of the n type impurity region14 and bottoms of the channel regions 4 are located at a substantiallyequal depth by the diffusion of the impurities.

The separated gate electrodes 13 a and 13 b are arranged symmetricallywith respect to the n type impurity region 14. That is, a centerline ofthe separation hole 12 substantially coincides with a centerline of then type impurity region 14 as indicated by an alternate long and shortdash line. Additionally, the gate width L_(g) is not more than a depthX_(ch) of the channel regions 4. In this manner, the n type impurityregion 14 having the side surfaces forming the junction surfacesubstantially perpendicular to the channel regions 4, and having theequal depth to that of the channel regions 4 is formed. Details thereofwill be described later. Additionally, a drain electrode is formed on aback surface of the substrate 1 although an illustration thereof isomitted. Note that, since the separated gate electrodes 13 a and 13 bare identical, the following description will be given by using the gateelectrode 13 a.

FIG. 1B is a cross-sectional view indicating a state of a depletionlayer 50 when drain-to-source voltage is applied in the OFF state. Notethat the interlayer insulating film 16 and the source electrode 18 areomitted in FIG. 1B.

In this embodiment, the side surfaces of the n type impurity region 14respectively form the junction surfaces substantially parallel to theside surfaces of the channel regions 4 adjacent thereto, and the bottomof the n type impurity region 14 and the bottoms of the channel regions4 are located substantially at an equal depth. That is, the channelregions 4 adjacent to each other are apart from each other not in amanner that cross-sectional shapes of edge portions of the respectivechannel regions 4 are in curved shapes with the edge portions havingcurvatures, rather in a manner that an equal distance between thechannel regions 4 is kept in vicinity of the top and in vicinity of thebottom. Additionally, the n type impurity region 14 is provided withconditions allowing the depletion layer 50, which extends from thechannel regions 4 in both sides thereof, to pinch off. Specifically, aratio of the separation width L_(KT) of the gate electrode 13 to thedepth X_(ch) of the channel regions 4 is set to 0.15 or less: 1.

In this manner, the depletion layer 50 inside the n type impurity region14 extends from the channel regions 4 in both sides thereof and pinchesoff as indicated by dashed lines, and thereby extends substantiallyevenly in a depth direction (vertical direction) of the substrate.

Conventionally, the depletion layer does not sufficiently pinch off inthe corner portion (the region “a” in FIG. 10) of each of the channelregions 24, whereby there arises a problem that a breakdown tends tooccur in the corner portion. However, in this embodiment, it is possibleto avoid this and to enhance a breakdown voltage of the MOSFET.

Additionally, distances between the channel regions 4 arranged with thegate electrode 13 interposed therebetween are uniform at the topsurfaces thereof and at the bottoms thereof, whereby the depletion layer50 sufficiently pinches off. Accordingly, it becomes possible toincrease an impurity concentration of the n type impurity region 14.That is, on-resistance reduction is achieved in the ON state of theMOSFET.

As described above, in this embodiment, the bottoms of the channelregions 4 and the bottom of the n type impurity region 14 are formed ina substantially same plane. Then, when the drain-to-source voltage isapplied in the OFF state of the MOSFET, the depletion layer 50 extendingfrom the channel regions 4 in the both sides thereof is allowed to pinchoff in the n type impurity region 14.

In the manner described above, it is possible to obtain a semiconductordevice ensuring a predetermined breakdown voltage and having a lowon-resistance in the ON state of the MOSFET.

Next, a second embodiment of the invention will be described.

As shown in FIGS. 1A and 1B (the first embodiment), respective junctionsurfaces of side surfaces of an n type impurity region 14 and channelregions 4 can be formed to be substantially perpendicular by setting thegate width L_(g) to be not more than the depth X_(ch) of the channelregions 4. Additionally, by allowing a depletion layer 50 to pinch offevenly inside the n type impurity region 14 in the depth (vertical)direction of the substrate, a predetermined breakdown voltage can beobtained.

In the second embodiment, more specifically, an MOSFET capable ofobtaining a predetermined breakdown voltage will be described. Notethat, because a structure thereof is the same as the one shown in FIGS.1A and 1B, the description will be given by referring to FIGS. 1A and1B.

In the second embodiment, a description will be given by taking as anexample a MOSFET to which a drain-to-source voltage not less than 600 Vcan be applied, i.e., a MOFSET realizing a breakdown voltage of 600 V orhigher.

As in the case with the first embodiment, in order to make a sidesurface of a n type impurity region 14 and a side surface of each of achannel regions 4 form a substantially perpendicular junction surface, agate length L_(g) is set to be not more than the depth X_(ch) of thechannel regions 4. Additionally, in order to equalize the depth of thechannel regions 4 and the depth of the n type impurity region 14, doseamounts of respective impurities are at levels comparable to each other.

In the second embodiment, a ratio of a separation width L_(KT) of a gateelectrode 13 to the depth X_(ch) of the channel region 4 (L_(KT):X_(ch)) is set to 0.15 or less: 1. To be more concrete, the separationwidth L_(KT) is set to 0.6 μm, and the depth X_(ch) of the channelregions 4 is set to 4 μm. Furthermore, a resistivity of an n− typeepitaxial layer 2 is set to a range of 15 Ω cm to 20 Ω cm.

By adopting the above-described conditions for the separation widthL_(KT) and the depth X_(ch) of the channel region 4, the depletion layer50 is fully pinched off, and a pn junction having a substantiallyperpendicular junction surface is obtained. Therefore, it is possible toincrease an impurity concentration of the n type impurity region 14 to1×10¹⁷ cm^(□3). Note that an impurity concentration of the channelregion 4 is also 1×10¹⁷ cm^(□3) in this case.

Specifically, in the ON state of the MOSFET, since the impurityconcentration of the n type impurity region 14 which is a region (theconventional π portion) serving as a current path just below the gateelectrode 13, is high, it is possible to allow a current through thecurrent path with a low resistance, and hence an on-resistance of theMOSFET can be reduced. On the other hand, in the OFF state of theMOSFET, the depletion layer 50 can be widened uniformly in the depthdirection of the substrate (vertically). Therefore, even in the casewhere a voltage of about 600 V is applied between the source and thedrain, it is possible to widen the depletion layer 50 uniformly in thedepth direction of (vertical direction to) the substrate. Specifically,the MOSFET having a low on-resistance as well as a high breakdownvoltage of about 600 V can be provided.

FIG. 2 is a chart showing a relation between the separation width L_(KT)and V_(DSS). Under the condition that the n type impurity region 14 isformed with a constant impurity concentration, the breakdown voltage(V_(DSS)) was evaluated while the separation width L_(KT) being varied.Note that a dose amount of the n type impurity region 14 is 1.5×10¹³cm⁻².

According to the above-described structure, if the separation widthL_(KT) is 0.6 μm or less, the depletion layer 50 is fully pinched off.Therefore, it is proved that the n type impurity region 14 with thebreakdown voltage of 600 V is obtained.

By referring to FIG. 3 to FIG. 9, a method of manufacturing the MOSFETof these embodiments will be described by taking a case of the secondembodiment as an example.

A method of manufacturing the semiconductor device of this embodimentcomprises: a step of forming a drain region by laminating a oneconductivity type semiconductor layer on a one conductivitysemiconductor substrate and of forming a first insulating film on theentire surface of the resultant structure; a step of forming a pluralityof gate electrodes on the first insulating film, at least part of whichare isolated from each other with a predetermined separation width; astep of implanting impurities of one conductivity type into a surface ofthe semiconductor layer between the plurality of gate electrodes;implanting impurities of an opposite conductivity type to oneconductivity type into a surface of the semiconductor layer outside theplurality of gate electrodes; a step of performing a thermal treatment,thus forming a plurality of channel regions and an impurity region ofone conductivity type having a junction surface approximatelyperpendicular to a side surface of each of the channel regions; a stepof forming a source region of one conductivity type in surfaces of thechannel regions; and a step of forming a second insulating film coveringthe plurality of gate electrodes wholly.

A first step (see FIG. 3):

An n− type epitaxial layer 2 is laminated on an n+ type siliconsemiconductor substrate 1, thus preparing a substrate serving as a drainregion 10. An entire surface of the resultant structure is thermallyoxidized at a temperature of about 1000° C., thus forming a gate oxidefilm 11 to a thickness of, for example, about 1000 Å in accordance witha threshold value of the MOSFET.

A second step (see FIG. 4):

A non-doped polysilicon layer is deposited on an entire surface of thegate oxide film 11, and phosphor (P), for example, is implanted anddiffused into the non-doped polysilicon layer at a high concentration,thus making the non-doped polysilicon layer highly conductive. By use ofa photoresist film (not shown) having a desired pattern as a mask, thepolysilicon film is subjected to dry etching, thus forming a gateelectrode 13. One cell of the MOSFET is composed of gate electrodes 13 aand 13 b, which have an equal gate width L_(g) and which are separatedfrom each other at last part of thereof by a separation hole 12.Specifically, the separation hole 12 is formed simultaneously with aformation of a pattern of the gate electrode 13, thus forming theseparated gate electrodes 13 a and 13 b. A width of the separation hole12, which is a separation width L_(KT), is equal to about 0.6 μm, forexample. Note that the gate electrode 13 may be formed in a way that animpurity doped polysilicon layer is deposited on the entire surface ofan insulating film 11 and then patterned. The patterning of the gateelectrode 13 and the formation of the separation hole 12 may be carriedout in different steps. Since the separated gate electrodes 13 a and 13b, which are separated from each other, have the same structure, thedescription of subsequent steps will be made by use of the separatedgate electrode 13 a.

The gate width L_(g) of the separated gate electrode 13 a is set to benot more than a depth of a channel region to be formed afterward, whichis, for example, about 2.0 μm.

A third step (see FIG. 5):

A photoresist film PR is formed on an entire surface of the resultantstructure, and then patterned so that the separation hole 12 and aperiphery of the separation hole 12 are exposed. N type impurities, forexample, phosphor P, are ion-implanted by use of the photoresist film PRas a mask. For example, a dose amount is about 1.0×10¹³ cm⁻², and anacceleration energy is 120 KeV. The n type impurities are implanted fromthe separation hole 12 into the surface of an n− type epitaxial layer 2through the gate oxidized film 11. Specifically, a surface region of then− type epitaxial layer 2 having a width approximately equal to theseparation width L_(KT), which is located just below the separation hole12, is an implantation region of the n type impurities, as shown in FIG.5.

A fourth step (see FIG. 6):

A photoresist film PR is formed again, and a portion in the photoresistfilm PR covering at least the separation hole 12 is left by use of aphotolithography process. P type impurities, for example, boron (B), areion-implanted into the surface of the n− type epitaxial layer 2 outsidethe gate electrode 13. Herein, a dose amount of the p type impurities inthe fourth step and the dose amount of the n type impurities in thethird step are approximately equal. For example, in the case of theboron, the boron impurities are ion-implanted under the condition thatthe acceleration energy is 80 KeV and the dose amount is 2×10¹³ cm⁻².The surface of the n− type epitaxial layer 2 outside both sides of thegate electrode 13 is an implantation region into which the p typeimpurities are implanted.

A Fifth step (see FIG. 7):

A thermal treatment is carried out at a temperature of 1150° C. for 180minutes, whereby the n type impurities and the p type impurities arediffused. Thus, channel regions 4 are formed in portions of a surface ofthe epitaxial layer 2 disposed on both sides of the gate electrode 13,and an n type impurity region 14 is formed below the separation hole 12.

The n type impurities implanted from the separation hole 12 are diffusedin a vertical direction with respect to the depth of the substrate, andsimultaneously are diffused in a lateral (horizontal) direction withrespect to the substrate. Specifically, by setting the gate length L_(g)of the separated gate electrode 13 a to be equal to or less than thedepth X_(ch) of the channel region 4, side surfaces of the n typeimpurity region 14 form junction surfaces substantially parallel to theside surfaces of the channel regions 4 adjacent thereto. Additionally, abottom of the n type impurity region 14 and bottoms of the channelregions 4 are located at depths substantially equal to each other by thediffusion of the impurities under the conditions of the fourth step.

Furthermore, a relation expressed by a ratio (the separation widthL_(KT): the depth X_(ch) of the channel region 4, which is equal to 0.15or less: 1) is adopted. To be more concrete, L_(KT) is set to 0.6 μm,and X_(ch) is set to 4 μm. Thus, a depletion layer can be fully pinchedoff in the n type impurity region 14.

Specifically, since it is possible to suppress a breakdown in thevicinity of the bottoms of the channel regions 4, the impurityconcentration of the n type impurity region 14 can be improved to behigher than that in the related arts. Accordingly, it is possible toreduce a resistance of a current path in the ON state of the MOSFET.

When the depth X_(ch) of the channel region 4 is formed to be furtherdeeper depending on characteristics of the MOSFET, the diffusion processis further carried out. Thus, though the width of the n type impurityregion 14 varies, there is no problem as long as the width thereof iswithin a range where the MOSFET can pinch off at the application ofV_(DSS).

A sixth step (see FIGS. 8A and 8B):

A mask exposing a part of the channel region 4 is formed by a newphotoresist film PR, n+ type impurities, for example, arsenic (As), areion-implanted. An acceleration energy is set to 100 KeV, and a doseamount is set to about 5×10¹⁵ cm⁻² (see FIG. 8A).

Thereafter, an insulating film 16′ such as PSG (Phosphorus SilicateGlass) serving as an interlayer insulating film is deposited by a CVDmethod. The n+ type impurities are diffused by a thermal treatment atthe time when the insulating film 16′ is formed, thus forming a sourceregion 15 (see FIG. 8A). The thermal treatment is carried out at atemperature lower than 1000° C. for about 60 minutes.

A sixth step (FIG. 9):

The insulating film 16′ is etched by use of a new photoresist film (notshown) as a mask, and an interlayer insulating film 16 is left, andsimultaneously contact holes CH are formed. The separated gateelectrodes 13 a and 13 b above the n type impurity region 14 are whollycovered with the interlayer insulating film 16.

Thereafter, a barrier metal (not shown) is formed on the entire surfaceof the resultant structure, and aluminum alloy is sputtered so as tohave a film thickness ranging from about 20000 Å to 50000 Å. An alloyingand thermal treatment is performed, thus forming a source electrode 18patterned to a desired pattern. Thus, a final structure shown in FIG. 1Ais obtained.

An n channel type MOSFET was described as the example in this embodimentof the present invention, and a p channel type MOSFET having an oppositeconductive type to the n channel type MOSFET can be similarly embodied.Preferred embodiments of the present invention are not limited to these.Specifically, preferred embodiments of the present invention can besimilarly embodied and the same effects can be achieved as long as thesemiconductor element is one of insulated gate type including an IGBT(Insulated Gate Bipolar Transistor) which is an insulated gate typebipolar transistor and in which a semiconductor layer having an oppositeconductivity type to the one conductivity type semiconductor substrate 1is disposed below the substrate 1.

According to preferred embodiments of the present invention, first, then type impurity region is provided, whereby the junction surface inwhich the side surface of the channel region is substantiallyperpendicular to the side surface of the n type impurity region can beformed. Accordingly, a width of an interval between the channel regionsis constant from the surface of the channel regions to the bottomthereof. Then, by forming the n type impurity region under the conditionthat the depletion layer extending from both sides of the channelregions is pinched off (with a certain impurity concentration and acertain width), the pinch-off of the depletion layer is sufficient evenin the bottom portion of the channel region. Thus, it is possible toavoid a breakdown in corner portions of the channel regions (regions “a”of FIG. 10).

To be more concrete, in the diffusion step of forming the channelregion, by setting the depth X_(ch) of the channel region to be not lessthan the gate length L_(g) of the separated gate electrodes of one cell,it is possible to provide the n type impurity region having the junctionsurface perpendicular to the side surface of the channel region andhaving the depth equal to that of the channel region.

Furthermore, by adopting a relation expressed by a ratio (the separationwidth L_(KT) of the separated gate electrodes: the depth X_(ch) of thechannel region, which is equal to or less than 0.6:4), it is possible toform the n type impurity region forming the junction surfaceperpendicular to the channel region, and it is possible to make thewidth of the n type impurity region equal to the width having a valuefor pinching off the depletion layer in the n type impurity region.Thus, the drain-to-source voltage V_(DSS) of not less than 600 V can beobtained. Furthermore, since the depletion layer is fully pinched offeven in the vicinity of the bottom portion of the channel region, it ispossible to increase the impurity concentration of the n type impurityregion up to 1×10¹⁷ cm⁻³. Hence, it is possible to achieve a lowresistance in the ON state of the MOSFET and an increase of thebreakdown voltage in the OFF state thereof.

Secondly, performing the ion-implantation of n type impurity region,after the formation of the gate electrode, the n type impurity region isformed in the diffusion step for forming the channel region. Thus, acontrol of the depth of the n type impurity region is made easierwithout being influenced by the thermal treatment during the formationof the gate electrode.

Furthermore, by controlling of the dose amount in the channel region andthe n type impurity region, it is possible to form the bottoms thereofto be substantially uniform. For example, boron is implanted into thechannel region under the condition that the acceleration energy is 80KeV and the dose amount is 2×10¹³ cm⁻², and phosphor is implanted intothe n type impurity region under condition that the acceleration energyis 120 KeV and the dose amount is 1×10¹³ cm⁻², and then the thermaltreatment is carried out at the temperature of 1150° C. Thus, thechannel region and the n type impurity region have the substantiallyuniform depth. In this case, though the n type impurity region has animpurity concentration, which is about 1×10¹⁷ cm⁻³ and is higher thanthat in the related art, the depletion layer is pinched off verticallyin the depth direction of the substrate. Thus, the predeterminedbreakdown voltage is obtained. For example, in this embodiment, in thecase where the resistivity p of the n type epitaxial layer ranges from15 Ω cm to 20 Ω cm, the drain-to-source breakdown voltage of not lessthan 600 V can be obtained.

1. A semiconductor device comprising: a semiconductor substrate of afirst general conductivity type; a semiconductor layer of the firstgeneral conductivity type disposed on a surface of the semiconductorsubstrate so as to provide a drain region; two channel regions of asecond general conductivity type disposed on the semiconductor layer; animpurity region of the first general conductivity type disposed betweenthe two channel regions, an junction interface between the impurityregion and one of the channel regions being perpendicular to the surfaceof the semiconductor substrate; an insulating film disposed on theimpurity region; a gate electrode disposed on the insulating film; and asource region of the first general conductivity type formed in a surfaceof each of the channel regions.
 2. The semiconductor device of claim 1,wherein a bottom of the impurity region and a bottom of each of thechannel regions are at a same level.
 3. The semiconductor device ofclaim 1, wherein the gate electrode comprises a first gate electrodeportion and a second gate electrode portion that are disposed on theimpurity region between the two channel regions, the first gateelectrode portion is at least partially separated from the second gateelectrode portion, and the first and second gate electrode portions arecovered by another insulating film.
 4. The semiconductor device of claim3, wherein a width of each of the first and second gate electrodeportions is equal to or less than a depth of the channel regions.
 5. Thesemiconductor device of claim 3, wherein a ratio of a separation widthbetween the first and second gate electrode portions to the depth of thechannel region is 0.15 or smaller.
 6. The semiconductor device of claim1, wherein the impurity region is configured to be pinched off bydepletion regions extending from the channel regions when a the gateelectrode and the source region are at a same electrical potential and areverse bias voltage is applied between the source and drain regions. 7.A method of manufacturing a semiconductor device, comprising: providinga device intermediate comprising a semiconductor substrate of a firstgeneral conductivity type, a semiconductor layer of the first generalconductivity type disposed on the semiconductor substrate and a firstinsulating film disposed on the semiconductor layer; forming a gateelectrode on the first insulating film; forming an impurity region ofthe first general conductivity type in the semiconductor layer under thegate electrode after the formation of the gate electrode; forming twochannel regions of a second general conductivity type in thesemiconductor layer so that the impurity region connects the two channelregions; forming a source region of the first general conductivity typein each of the channel regions; and forming a second insulating filmcovering the gate electrode.
 8. A method of manufacturing asemiconductor device, comprising: providing a device intermediatecomprising a semiconductor substrate of a first general conductivitytype, a semiconductor layer of the first general conductivity typedisposed on a surface of the semiconductor substrate and a firstinsulating film disposed on the semiconductor layer; forming on thefirst insulation film a gate electrode having an opening therein;implanting a first impurity for the first general conductivity type intopart of the semiconductor layer through the opening of the gateelectrode; implanting a second impurity for the second generalconductivity type into part of the semiconductor layer that is outsidethe gate electrode; heating the device intermediate so that the firstand second impurities are diffused so as to form an impurity region anda channel region that have an junction interface perpendicular to thesurface of the semiconductor substrate; forming a source region of thefirst general conductivity type in the channel region; and forming asecond insulating film covering the gate electrode.
 9. The method ofclaim 8, wherein a width of the gate electrode between the opening andan edge of the gate electrode is equal to or less than a depth of thechannel region.
 10. The method of claim 7, wherein the impurity regionand the channel regions have an equal impurity concentration.
 11. Themethod of claim 8, wherein the impurity region and the channel regionhave an equal impurity concentration.
 12. The method of claim 10,wherein the equal impurity concentration is about 1×10¹⁷ cm⁻³.
 13. Themethod of claim 11, wherein the equal impurity concentration is about1×10¹⁷ cm⁻³.
 14. The method of claim 8, wherein the opening of the gateelectrodes creates a separation of two parallel portions of the gateelectrode, a ratio of a separation width between the two parallelportions to a depth of the channel region is 0.15 or smaller.
 15. Themethod of claim 7, wherein a bottom of the impurity region and a bottomof each of the channel regions are at a same level.
 16. The method ofclaim 8, wherein a bottom of the impurity region and a bottom of thechannel region are at a same level.
 17. The method of claim 8, whereinthe source region is formed by an ion implantation and a diffusion. 18.A semiconductor device comprising: a semiconductor substrate of a firstgeneral conductivity type; a semiconductor layer of the first generalconductivity type disposed on a surface of the semiconductor substrateso as to provide a drain region; two channel regions of a second generalconductivity type disposed on the semiconductor layer; an impurityregion of the first general conductivity type disposed between the twochannel regions so as to connect the two channel regions; an insulatingfilm disposed on the impurity region; a gate electrode disposed on theinsulating film and comprising a first gate electrode portion and asecond gate electrode portion that are disposed on the impurity regionbetween the two channel regions, the first gate electrode portion beingat least partially separated from the second gate electrode portion; anda source region of the first general conductivity type formed in asurface of each of the channel regions.
 19. A semiconductor devicecomprising: a semiconductor substrate of a first general conductivitytype; a semiconductor layer of the first general conductivity typedisposed on a surface of the semiconductor substrate so as to provide adrain region; two channel regions of a second general conductivity typedisposed on the semiconductor layer, each of the channel regions beingelongated in a direction; an impurity region of the first generalconductivity type disposed between the two elongated channel regions,the impurity region being elongated in the direction; an insulating filmdisposed on the elongated impurity region and channel regions; a gateelectrode disposed on the insulating film and having a slit elongated inthe direction but not reaching an edge portion of the gate electrode;and a source region of the first general conductivity type formed in asurface of each of the channel regions.